AMAZING WORKS HERE - Drive an Industry Forward
Step inside our world and you'll find one brilliant mind after another working together in a spirit of collaboration that is simply contagious. And through this shared dedication-this culture of innovation and exploration-we do more than deliver the latest technologies. We deliver the future.
That's where you come in. We need innovators and proven communicators like you to push our thinking. We need your strong collaboration and organizational skills, as well as your ability to effectively work with and manage teams. You will help push us to the next level. Joining Intel’s Perceptual Computing team means joining a dynamic team at a company that has established a reputation for innovation.
We are looking for an experienced Static Timing Analysis Engineer with extensive experience of the latest digital design flows, to join our Chip Create team based in either Dublin, Ireland or Timisoara, Romania. .
Responsibilities
Working with Systems and Application teams to drive timing closure friendly SoC architecture and IO interfaces/IO pin.
Full chip timing constraints development, full chip Static Timing Analysis and Signoff for a complex, multi-clock, multi-voltage SoC.
Streamlining the timing signoff criteria, timing analysis methodologies and flows and develop/enhance auto ECO generation scripts for timing closure.
Analyse and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow.
Enhance existing entire timing flow from frontend (pre-layout) to backend (post-layout) at both block level and chip level.
Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level).
Actively work as part of team both locally & also with remote or multi-site teams.
Required skills:
5-10 years relevant experience.
University degree, postgraduate qualifications desirable.
Extensive Synthesis, DFT and floor-planning experience.
Extensive Static timing analysis with Signal Integrity experience.
Experience with STA timing closure and interfacing with the Physical design team.
Experience with low power design techniques including low power synthesis and power island implementation.
Experience with Synopsys and/or Cadence tools and design flows is essential especially with Synthesis, DFT, BIST insertion and timing analysis.
Desired skills:
Experience in debugging ATPG patterns, compressed ATPG patterns, MBIST, and JTAG related issues
Knowledge of Verilog HDL, System Verilog, VHDL, Python, TCL, Perl, C, C++, Matlab
What We Offer You
When you come to work at Intel, you come to work in a collaborative, supportive environment, where your equally brilliant colleagues will push you to be your best. There's no fear of failure-we know that's how innovation happens. And you'll never be bored. We also offer:
-Competitive benefits and pay (including bonuses)
-Opportunities for professional development and continuing education
-The flexibility you need to achieve balance
Intel fosters a collaborative environment allowing the brightest minds in the world to come together to achieve exceptional results.
Inside this Business Group
Employees of the Perceptual Computing Group have an exciting opportunity before them. We are the heart and soul of innovation at Intel, creating the technologies that will shape the future of computing.
Perceptual Computing drives the sensification of computing…Intel’s RealSense. We research, develop, produce and deploy advanced computing solutions based on natural sensing and interactions, intuitive interfaces, immersive applications and user experiences. RealSense technology is charting new territory in perceptual computing by sensing, understanding, interacting and learning in ways that will revolutionize the way we solve problems – in both consumer and enterprise markets.
http://career.intel.com/XELvG
