Sorry, but this job has expired. Please try another search or browse our jobs.

Senior Static Timing Analysis Engineer

Job Category:
Software Developer/Engineer, QA/Tester
Job Type:
Level of IT Experience:
5-10 Years
Central Dublin
Dublin city centre
Salary Description:
Emtech Recruitment
Job Ref:

Senior Static Timing Analysis Engineer with extensive experience of the latest digital design flows required for permanent role with leading multinational in Dublin city centre.

• Working with Systems and Application teams to drive timing closure friendly SoC architecture and IO interfaces/IO pin.
• Full chip timing constraints development, full chip Static Timing Analysis and Signoff for a complex, multi-clock, multi-voltage SoC.
• Streamlining the timing signoff criteria, timing analysis methodologies and flows and develop/enhance auto ECO generation scripts for timing closure.
• Analyse and incorporate advance timing signoff flows (SSTA, LOCV Based STA, IR Drop aware STA) into SoC timing signoff flow.
• Enhance existing entire timing flow from frontend (pre-layout) to backend (post-layout) at both block level and chip level.
• Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level).
• Actively work as part of team both locally & also with remote or multi-site teams.

• 5-10 years relevant experience.
• University Degree, postgraduate qualifications desirable.
• Extensive Synthesis, DFT and floor-planning experience.
• Extensive Static timing analysis with Signal Integrity experience.
• Experience with STA timing closure and interfacing with the Physical design team.
• Experience with low power design techniques including low power synthesis and power island implementation.
• Experience with Synopsys and/or Cadence tools and design flows is essential especially with Synthesis, DFT, BIST insertion and timing analysis

• Experience in debugging ATPG patterns, compressed ATPG patterns, MBIST, and JTAG related issues
• Knowledge of Verilog HDL, System Verilog, VHDL, Python, TCL, Perl, C, C++, Matlab

Please contact Emer Moore to discuss in confidence

Contact Details:
Emtech Recruitment
Tel: 353 (0)57 863 8188
Contact: Emer Moore

You may return to your current search results by clicking here.

This website uses cookies. Read our cookie policy for more information. By continuing to browse this site you are agreeing to our use of cookies.

Latest Job Listings