Defining and executing DFx architectures that meet the Test and Debug needs of the SOCs & IPs under development. This includes meeting the manufacturing, quality, debug, and all internal & external customer requirements. 
Hands-on implementation in RTL Integration, Validation and HVM Pattern development. 
Collaborating with other SoC architects in the Intel SOC community to ensure the SOC/IP under development meets SOC (Chassis ) requirements 
Working with functional IP owners to ensure that the IP includes all the required Dfx hooks to support features like Scan and VISA , and follows the necessary IP Delivery guidelines. 
Authoring technical architectural specifications (EAS, MAS) 
Collaborating and providing leadership during platform, RTL, and software/firmware development and validation (both pre- and post-silicon), 

Proven experience with DFX architecture and implementation 
Strong knowledge of DFT architectures & methodologies. This includes Scan, ATPG and Mbist, IO DFx. 
Proven knowledge of Verilog & System Verilog, RTL design and micro-architecture skills. 
Strong knowledge of SoC tools/methodology (Collage, OVM, Saola, ACE, VCS*, RDL/EAS, Lintra, CDC, Synthesis, Spyglass). 
Strong debug skills and demonstrated experiences in Perl & TCL scripting. 
Strong Communications skills and the ability to lead/direct cross functional teams. 

Candidate must have a BSEE/MSEE + 3 years of relevant experience.